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ltc3805-5 1 38055fe features description adjustable frequency current mode flyback/ boost/sepic dc/dc controller the ltc ? 3805-5 is a current mode dc/dc controller de - signed to drive an n-channel mosfet in fyback, boost and sepic converter applications. operating frequency and slope compensation can be programmed by external resistors. programmable overcurrent sensing protects the converter from overload and short-circuit conditions. soft-start can be programmed using an external capacitor and the soft-start capacitor also programs an automatic restart feature. the ltc3805-5 provides 1.5% output voltage accuracy and consumes only 360a of quiescent current during normal operation and only 40a during micropower start- up. using a 9.5v internal shunt regulator, the ltc3805-5 can be powered from a high v in through a resistor or it can be powered directly from a low impedance dc voltage from 4.7v to 8.8v. the ltc3805-5 is available in the 10-lead msop package and the 3mm 3mm dfn package. l , lt, ltc, ltm, burst mode, linear technology and the linear logo are registered trademarks, no r sense and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 5v to 12v/1a boost converter typical application n v in and v out limited only by external components n 4.5v undervoltage lockout threshold n adjustable slope compensation n adjustable overcurrent protection with automatic restart n adjustable operating frequency (70khz to 700khz) with one external resistor n synchronizable to an external clock n 1.5% reference accuracy n only 100mv current sense voltage drop n run pin with precision threshold and adjustable hysteresis n programmable soft-start with one external capacitor n low quiescent current: 360a n small 10-lead msop and 3mm 3mm dfn applications n automotive power supplies n telecom power supplies n isolated electronic equipment n auxiliary/housekeeping power supplies n power over ethernet effciency and power loss vs load current ltc3805-5 gnd i th run gate oc i sense ssflt fs fb v cc 118k 3k 8m 22f 2 sync 1.33k 4.3h ups840 v in 5v v out 12v 1a 13.7k 191k 100f 38055 ta01a 0.1f 20k 470pf load current (a) 0.01 efficiency (%) power loss (w) 85 90 38055ta01b 80 75 0.1 1 10 100 95 1 1.5 0.5 0 2.5 2.0 5v efficiency 5v loss 8.5v loss 8.5v efficiency
ltc3805-5 2 38055fe absolute maximum ratings v cc to gnd low impedance source ........................ C0.3v to 8.8v current fed ........................................ 25ma into v cc * sync ........................................................... C0.3v to 6v ssflt ........................................................... C0.3v to 5v fb, i th , fs ................................................. C0.3v to 3.5v run ........................................................... C0.3v to 18v (note 1) oc, i sense .................................................... C0.3v to 1v operating junction temperature range (notes 2, 3) ........................................... C55c to 150c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) mse package .................................................... 300c *ltc3805-5 internal clamp circuit regulates v cc voltage to 9.5v top view dd package 10-lead (3mm 3mm) plastic dfn 10 11 9 6 7 8 4 5 3 2 1 gate v cc oc i sense sync ssflt i th fb run fs t jmax = 125c, ja = 45c/w exposed pad (pin 11) is gnd, must be connected to gnd 1 2 3 4 5 ssflt i th fb run fs 10 9 8 7 6 gate v cc oc i sense sync top view mse package 10-lead plastic msop 11 t jmax = 125c, ja = 45c/w exposed pad (pin 11) is gnd, must be connected to gnd pin configuration lead free finish tape and reel part marking* package description temperature range ltc3805emse-5#pbf ltc3805emse-5#trpbf ltdgx 10-lead plastic msop C40c to 85c ltc3805imse-5#pbf ltc3805imse-5#trpbf ltdgx 10-lead plastic msop C40c to 125c ltc3805hmse-5#pbf ltc3805hmse-5#trpbf ltdgx 10-lead plastic msop C40c to 150c ltc3805mpmse-5#pbf ltc3805mpmse-5#trpbf ltdgx 10-lead plastic msop C55c to 150c ltc3805edd-5#pbf ltc3805edd-5#trpbf ldhb 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc3805idd-5#pbf ltc3805idd-5#trpbf ldhb 10-lead (3mm 3mm) plastic dfn C40c to 125c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. consult ltc marketing for information on lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ order information
ltc3805-5 3 38055fe symbol parameter conditions min typ max units v turnon v cc turn-on voltage v cc rising l 4.3 4.5 4.7 v v turnoff v cc turn-off voltage v cc falling l 3.75 3.95 4.15 v v hyst v cc hysteresis 0.55 v v clamp1ma v cc shunt regulator voltage i cc = 1ma, v run = 0 l 8.8 9.25 9.65 v v clamp25ma v cc shunt regulator voltage i cc = 25ma, v run = 0 l 8.9 9.5 9.9 v i cc input dc supply current normal operation (f osc = 200khz) (note 4) 360 a v run < v runon or v cc < v turnon C 100mv (micropower start-up) l 40 90 a v runon run turn-on voltage v cc = v turnon + 100mv l 1.122 1.207 1.292 v v runoff run turn-off voltage v cc = v turnon + 100mv l 1.092 1.170 1.248 v i run(hyst) run hysteresis current l 4 5 5.8 a v fb regulated feedback voltage 0c t j 85c (e-grade) (note 5) C40c t j 85c (e-grade) (note 5) C40c t j 125c (i-grade) (note 5) C40c t j 150c (h-grade) (note 5) C55c tj 150c (mp-grade) l l l l 0.788 0.780 0.780 0.770 0.770 0.800 0.800 0.800 0.800 0.800 0.812 0.812 0.812 0.820 0.820 v v v v v i fb v fb input current v ith = 1.3v (note 5) 20 na g m error amplifer transconductance i th pin load = 5a (note 5) 333 a/v dv o(line) output voltage line regulation v turnoff < v cc < v clamp1ma (note 5) 0.05 mv/v dv o(load) output voltage load regulation i th sinking 5a (note 5) i th sourcing 5a (note 5) 3 3 mv/a mv/a f osc oscillator frequency r fs = 350k 70 khz r fs = 36k 700 khz dc on(min) minimum switch-on duty cycle f osc = 200khz 6 9 % dc on(max) maximum switch-on duty cycle f osc = 200khz 70 80 95 % f sync as a function of f osc 70khz < f osc < 700khz, 70khz < f sync < 700khz 67 133 % v sync minimum sync amplitude 2.9 v i ss soft-start current C6 a i fto fault timeout current 2 a t ss(int) internal soft-start time no external capacitor on ssflt 1.8 ms t fto(int) internal fault timeout no external capacitor on ssflt 4.5 ms t rise gate drive rise time c load = 3000pf 30 ns t fall gate drive fall time c load = 3000pf 30 ns v i(max) peak current sense voltage r sl = 0 (note 6) l 85 100 115 mv i sl(max) peak slope compensation output current (note 7) 10 a v oct overcurrent threshold r oc = 0 (note 8) l 85 100 115 mv i oc overcurrent threshold adjust current 10 a electrical characteristics the l denotes the specifcations which apply over the specifed operating junction temperature range, otherwise specifcations are at t a = 25c, v cc = 5v, unless otherwise noted (note 2).
ltc3805-5 4 38055fe electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3805-5 is tested under pulsed conditions such that t j t a . the ltc3805e-5 is guaranteed to meet specifcations from 0c to 85c. specifcations over the C40c to 85c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3805i-5 is guaranteed over the C40c to 125c operating junction temperature range, the ltc3805h-5 is guaranteed over the full C40c to 150c operating junction temperature range and the ltc3805mp-5 is tested and guaranteed over the full C55c to 150c operating temperature range. high junction temperatures degrade operating lifetimes. operating lifetime is derated at junction temperatures greater than 125c. note that the maximum ambient temperature consistent with these specifcations is determined by specifc operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ? 45c/w) note 4: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. note 5: the ltc3805-5 is tested in a feedback loop that servos v fb to the output of the error amplifer while maintaining i th at the midpoint of the current limit range. note 6: peak current sense voltage is reduced dependent on duty cycle and an optional external resistor in series with the sense pin. for details, refer to programmable slope compensation in the applications information section. note 7: guaranteed by design. note 8: overcurrent threshold voltage is reduced dependent on an optional external resistor in series with the oc pin. for details, refer to programmable overcurrent in the applications information section.
ltc3805-5 5 38055fe temperature (c) ?75 ?50 788 v fb voltage (mv) 792 800 808 796 804 812 ?25 0 25 50 38055 g01 75 100 150125 typical performance characteristics reference voltage vs temperature reference voltage vs supply voltage oscillator frequency vs r fs oscillator frequency vs supply voltage oscillator frequency vs temperature run undervoltage lockout thresholds vs temperature run hysteresis current vs temperature v cc undervoltage lockout thresholds vs temperature r fs (k) 0 f osc (khz) 400 500 600 400 38055 g03 300 200 0 100 200 300 100 800 700 v cc (v) 4 0.799700 v fb (v) 0.799800 0.799900 0.800000 0.800100 0.800200 0.800300 6 8 5 7 9 10 38055 g02 v cc (v) 4 201 202 203 8 38055 g04 200 199 5 6 7 9 198 197 196 f osc (khz) r fs = 124k temperature (c) 198 oscillator frequency (khz) 199 200 201 202 38055 g05 r fs = 124k ?75 ?50 ?25 0 25 50 75 100 150125 ?75 ?50 ?25 0 25 50 75 100 150125 temperature (c) 1.170 run voltage (v) 1.175 1.185 1.195 1.180 1.190 1.200 1.205 38055 g06 v run(on) v run(off) ?75 ?50 ?25 0 25 50 75 100 150125 temperature (c) 4.70 i run(hyst) 4.80 5.00 4.90 5.10 5.20 38055 g07 ?75 ?50 ?25 0 25 50 75 100 150125 temperature (c) 3.0 v cc undervoltage lockout (v) 3.5 4.5 4.0 5.0 38055 g08 v turn(on) v turn(off)
ltc3805-5 6 38055fe start-up i cc supply current vs temperature i cc supply current vs temperature v cc shunt regulator voltage vs temperature peak current sense voltage vs temperature overcurrent threshold vs temperature internal soft-start time vs temperature external soft-start current vs temperature external timeout current vs temperature typical performance characteristics ?75 ?50 ?25 0 25 50 75 100 150125 temperature (c) 30 start-up supply current (a) 32 36 44 34 40 48 50 38 42 46 38055 g09 ?75 ?50 ?25 0 25 50 75 100 150125 temperature (c) 300 supply current (a) 310 330 320 340 360 350 38055 g10 ?75 ?50 ?25 0 25 50 75 100 150125 temperature (c) 9.20 v clamp (v) 9.25 9.35 9.45 9.30 9.40 9.50 9.55 9.60 38055 g11 v clamp25ma v clamp1ma temperature (c) 99.0 peak current sense voltage (mv) 99.2 99.6 100.0 99.4 99.8 100.2 100.4 100.8 100.6 38055 g12 ?75 ?50 ?25 0 25 50 75 100 150125 ?75 ?50 ?25 0 25 50 75 100 150125 temperature (c) 94 overcurrent threshold (mv) 96 100 98 102 104 38055 g13 ?75 ?50 ?25 0 25 50 75 100 150125 temperature (c) 1.90 internal soft-start time (ms) 1.95 2.05 2.15 2.00 2.10 2.20 38055 g14 ?75 ?50 ?25 0 25 50 75 100 150125 temperature (c) 4.4 4.5 i ss soft-start current (a) 4.6 4.8 5.0 4.7 4.9 5.1 5.2 5.4 5.3 38055 g15 ?75 ?50 ?25 0 25 50 75 100 150125 temperature (c) 1.5 i fto external timeout current (a) 1.6 1.8 2.0 1.7 1.9 2.1 38055 g16
ltc3805-5 7 38055fe block diagram pin functions ssflt (pin 1): soft-start pin. a capacitor placed from this pin to gnd (exposed pad) controls the rate of rise of converter output voltage during start-up. this capacitor is also used for time out after a fault prior to restart. i th (pin 2): error amplifer compensation point. normal operating voltage range is clamped between 0.7v and 1.9v. fb (pin 3): receives the feedback voltage from an external resistor divider across the output. run (pin 4): an external resistor divider connects this pin to v in and sets the thresholds for converter operation. fs (pin 5): a resistor connected from this pin to ground sets the frequency of operation. sync (pin 6): input to synchronize the oscillator to an external source. i sense (pin 7): performs two functions: for current mode control, it monitors the switch current, using the voltage across an external current sense resistor. pin 7 also injects a current ramp that develops slope compensation voltage across an optional external programming resistor. oc (pin 8): overcurrent pin. connect this pin to the ex - ternal switch current sense resistor. an additional resistor programs the overcurrent trip level. v cc (pin 9): supply pin. a capacitor must closely decouple v cc to gnd (exposed pad). gate (pin 10): gate drive for the external n-channel mosfet. this pin swings from gnd to v cc . gnd (exposed pad pin 11): ground. a capacitor must closely decouple gnd to v cc (pin 9). the exposed pad must be soldered to electrical ground on pcb for electrical contact and rated thermal performance. ? + ? + ? + slope comp current ramp v cc run gate driver gate 7 isense 38055 bd oscillator q r current comparator overcurrent comparator shutdown shutdown i th clamps s 20mv i th error amplifier fb soft-start ramp 10a 100mv switching logic and blanking circuit 10 3 ssflt 1 oc 8 gnd 1.2v 11 2 sync fs 5 6 9 4 undervoltage lockout 800mv reference soft-start fault
ltc3805-5 8 38055fe operation the ltc3805-5 is a programmable-frequency current mode controller for fyback, boost and sepic dc/dc converters. the ltc3805-5 is designed so that none of its pins need to come in contact with the input or output voltages of the power supply circuit of which it is a part, allowing the conversion of voltages well beyond the ltc3805-5s absolute maximum ratings. main control loop please refer to the block diagram of this data sheet and the typical application shown on the front page. an ex - ternal resistive voltage divider presents a fraction of the output voltage to the fb pin. the divider is designed so that when the output is at the desired voltage, the fb pin voltage equals the 800mv internal reference voltage. if the load current increases, the output voltage decreases slightly, causing the fb pin voltage to fall below the 800mv reference. the error amplifer responds by feeding current into the i th pin causing its voltage to rise. conversely, if the load current decreases, the fb voltage rises above the 800mv reference and the error amplifer sinks current away from the i th pin causing its voltage to fall. the voltage at the i th pin controls the pulse-width modula - tor formed by the oscillator, current comparator and sr latch. specifcally, the voltage at the i th pin sets the cur - rent comparators trip threshold. the current comparators i sense input monitors the voltage across an external current sense resistor in series with the source of the external mosfet. at the start of a cycle, the ltc3805-5s oscillator sets the sr latch and turns on the external power mosfet. the current through the external power mosfet rises as does the voltage on the i sense pin. the ltc3805-5s cur - rent comparator trips when the voltage on the i sense pin exceeds a voltage proportional to the voltage on the i th pin. this resets the sr latch and turns off the external power mosfet. in this way, the peak current levels through the external mosfet and the fyback transformers primary and secondary windings are controlled by the voltage on the i th pin. if the current comparator does not trip, the ltc3805-5 automatically limits the duty cycle to 80%, resets the sr latch, and turns off the external mosfet. the path from the fb pin, through the error amplifer, current comparator and the sr latch implements the closed-loop current mode control required to regulate the output voltage against changes in input voltage or output current. for example, if the load current increases, the output voltage decreases slightly, and sensing this, the error amplifer sources current from the i th pin, raising the current comparator threshold, thus increasing the peak currents through the transformer primary and secondary. this delivers more current to the load and restores the output voltage to the desired level. the i th pin serves as the compensation point for the control loop. typically, an external series rc network is connected from i th to ground and is chosen for optimal response to load and line transients. the impedance of this rc network converts the output current of the error amplifer to the i th voltage which sets the current comparator threshold and commands considerable infuence over the dynamics of the voltage regulation loop.
ltc3805-5 9 38055fe figure 1. start-up/shutdown state diagram ltc3805-5 shutdown ltc3805-5 fault timeout 38055 f01 v run > v runon and v cc > v turnon v run < v runoff v cc < v turnoff v ssflt < 0.7v v oc > 100mv ltc3805-5 enabled operation start-up/shutdown the ltc3805-5 has two shutdown mechanisms to disable and enable operation: an undervoltage lockout on the v cc supply pin voltage, and a precision-threshold run pin. the voltage on both pins must exceed the appropriate threshold before operation is enabled. the ltc3805-5 transitions into and out of shutdown according to the state diagram shown in figure 1. operation in fault timeout is discussed in a subsequent section. during shutdown the ltc3805-5 draws only a small 40a current. the undervoltage lockout (uvlo) mechanism prevents the ltc3805-5 from trying to drive the external mosfet gate with insuffcient voltage on the v cc pin. the voltage at the v cc pin must initially exceed v turnon = 4.5v to en - able ltc3805-5 operation. after operation is enabled, the voltage on the v cc pin may fall as low as v turnoff = 4v before undervoltage lockout disables the ltc3805-5. see the applications information section for more detail. the run pin is connected to the input voltage using a voltage divider. converter operation is enabled when the voltage on the run pin exceeds v runon = 1.207v and disabled when the voltage falls below v runoff = 1.170v. additional hysteresis is added by a 5a current source acting on the voltage dividers thevenin resistance. setting the input voltage range and hysteresis is further discussed in the applications information section. setting the oscillator frequency connect a frequency set resistor r fs from the fs pin to ground to set the oscillator frequency over a range from 70khz to 700khz. the oscillator frequency is calculated from: f osc = 24 ? 10 9 r fs ? 1500 the oscillator may be synchronized to an external clock using the sync input. the rising edge of the external clock on the sync pin triggers the beginning of a switching period, i.e., the gate pin going high. the pulse width of the external clock is quite fexible. overcurrent protection with the oc pin connected to the external mosfets current sense resistor, the converter is protected in the event of an overload or short-circuit on the output. during normal operation the peak value of current in the external mosfet, as measured by the current sense resistor (plus any adjust - ment for slope compensation), is set by the voltage on the i th pin operating through the current comparator. as the output current increases, so does the voltage on the i th pin and so does the peak mosfet current.
ltc3805-5 10 38055fe operation first, consider operation without overcurrent protection. for some maximum converter output current, the voltage on the i th pin rises to and is clamped at approximately 1.9v. this corresponds to a 100mv limit on the voltage at the i sense pin. as the output current is further increased, the duty cycle is reduced as the output voltage sags. however, the peak current in the external mosfet is limited by the 100mv threshold at the i sense pin. as the output current is increased further, eventually, the duty cycle is reduced to the 6% minimum. since the external mosfet is always turned on for this minimum amount of time, the current comparator no longer limits the current through the external mosfet based on the 100mv threshold. if the output current continues to in - crease, the current through the mosfet could rise to a level that would damage the converter. to prevent damage, the overcurrent pin, oc, is also connected to the current sense resistor, and a fault is triggered if the voltage on the oc pin exceeds 100mv. to protect itself, the converter stops operating as described in the next section. external resistors can be used to ad - just the overcurrent threshold to voltages higher or lower than 100mv as described in the applications information section. soft-start and fault timeout operation the soft-start and fault timeout of the ltc3805-5 uses either a fxed internal timer or an external timer programmed by a capacitor from the ssflt pin to gnd. the internal soft-start and fault timeout times are minimums and can be increased by placing a capacitor from the ssflt pin to gnd. operation is shown in figure 1. leave the ssflt pin open to use the internal soft-start and fault timeout. the internal soft-start is complete in about 1.8ms. in the event of an overcurrent as detected by the oc pin exceeding 100mv, the ltc3805-5 shuts down and an internal timing circuit waits for a fault timeout of about 4.25ms and then restarts the converter. add a capacitor c ss from the ssflt pin to gnd to increase both the soft-start time and the time for fault timeout. dur - ing soft-start, c ss is charged with a 6a current. when the ltc3805-5 comes out of shutdown, the ltc3805-5 quickly charges c ss to about 0.7v at which point gate begins switching. from that point, gate continues switching with increasing duty cycle until the ssflt pin reaches about 2.25v at which point soft-start is over and closed-loop regulation begins. the voltage on the ssflt pin addition - ally further charges to about 4.75v. c ss also performs the timeout function in the event of a fault. after a fault, c ss is slowly discharged from about 4.75v to about 0.7v by a 2a current. when the voltage on the ssflt pin reaches 0.7v the converter attempts to restart. more detail on programming the external soft-start fault timeout is described in the applications information section. powering the ltc3805-5 a built-in shunt regulator from the v cc pin to gnd limits the voltage on the v cc pin to approximately 9.5v as long as the shunt regulator is not forced to sink more than 25ma. the shunt regulator is always active, even when the ltc3805-5 is in shutdown, since it serves the vital function of protecting the v cc pin from overvoltage. the shunt regulator permits the use of a wide variety of pow - ering schemes for the ltc3805-5 even from high voltage sources that exceed the ltc3805-5s absolute maximum ratings. further details on powering schemes are described in the applications information section. adjustable slope compensation the ltc3805-5 injects a 10a peak current ramp out of its i sense pin which can be used, in conjunction with an external resistor, for slope compensation in designs that require it. this current ramp is approximately linear and begins at zero current at 6% duty cycle, reaching peak current at 80% duty cycle. additional details are provided in the applications information section.
ltc3805-5 11 38055fe applications information many ltc3805-5 application circuits can be derived from the topologies shown on the frst page or in the typical applications section of this data sheet. the ltc3805-5 itself imposes no limits on allowed input voltage v in or output voltage v out . these are all determined by the ratings of the external power components. in figure 8, the factors are: q1 maximum drain-source voltage (b vdss ), on-resistance (r ds(on) ) and maximum drain current, t1 saturation fux level and winding insulation breakdown voltages, c in and c out maximum working voltage, equiva - lent series resistance (esr), and maximum ripple current ratings, and d1 and r sense power ratings. v cc bias power the v cc pin must be bypassed to the gnd pin with a minimum 1f ceramic or tantalum capacitor located im - mediately adjacent to the two pins. proper supply bypassing is necessary to supply the high transient currents required by the mosfet gate driver. for maximum fexibility, the ltc3805-5 is designed so that it can be operated from voltages well beyond the ltc3805-5s absolute maximum ratings. figure 2 shows the simplest case, in which the ltc3805-5 is powered with a resistor r vcc connected between the input voltage and v cc . the built-in shunt regulator limits the voltage on the v cc pin to around 9.5v as long as the internal shunt regulator is not forced to sink more than 25ma. this pow - ering scheme has the drawback that the power loss in the resistor reduces converter effciency and the 25ma shunt regulator maximum may limit the maximum-to-minimum range of input voltage. the typical application circuit in figure 9 shows a different fyback converter bias power strategy for a case in which neither the input or output voltage is suitable for providing bias power to the ltc3805-5. a small npn preregulator transistor and a zener diode are used to accelerate the rise of v cc and reduce the value of the v cc bias capacitor. the fyback transformer has an additional bias winding to provide bias power. note that this topology is very power - ful because, by appropriate choice of transformer turns ratio, the output voltage can be chosen without regard to the value of the input voltage or the v cc bias power for the ltc3805-5. the number of turns in the bias winding is chosen according to n bias = n sec v cc + v d2 v out + v d1 where n bias is the number of turns in the bias winding, n sec is the number of turns in the secondary winding, v cc is the desired voltage to power the ltc3805-5, v out is the converter output voltage, v d1 is the forward voltage drop of d1 and v d2 is the forward voltage drop of d2. note that since v out is regulated by the converter control loop, v cc is also regulated although not as precisely. if an off-the-shelf transformer with excessive bias windings is used, the resistor, r bias in figure 9, can be added to limit the current. transformer design considerations transformer specifcation and design is perhaps the most critical part of applying the ltc3805-5 successfully. in addition to the usual list of caveats dealing with high fre - quency power transformer design, the following should prove useful. turns ratios due to the use of the external feedback resistor divider ratio to set output voltage, the user has relative freedom in selecting transformer turns ratio to suit a given ap - plication. simple ratios of small integers, e.g., 1:1, 2:1, 3:2, etc. can be employed which yield more freedom in setting total turns and transformer inductance. simple integer turns ratios also facilitate the use of off-the-shelf confgurable transformers. turns ratio can be chosen on figure 2. powering the ltc3805-5 via the internal shunt regulator ltc3805-5 v cc r vcc c vcc 38055 f02 v in gnd
ltc3805-5 12 38055fe applications information the basis of desired duty cycle. however, remember that the input supply voltage plus the secondary-to-primary referred version of the fyback pulse (including leakage spike) must not exceed the allowed external mosfet breakdown rating. leakage inductance transformer leakage inductance (on either the primary or secondary) causes a voltage spike to occur after the turn off of mosfet (q1) in figure 8. this is increasingly prominent at higher load currents, where more stored energy must be dissipated. in some cases an rc snubber circuit will be required to avoid overvoltage breakdown at the mosfets drain node. application note 19 is a good reference on snubber design. a biflar or similar winding technique is a good way to minimize troublesome leak - age inductances. however, remember that this will limit the primary-to-secondary breakdown voltage, so biflar winding is not always practical. setting undervoltage and hysteresis on v in the run pin is connected to a resistive voltage divider connected to v in as shown in figure 3. the voltage thresh - old for the run pin is v runon rising and v runoff falling. note that v runon C v runoff = 35mv of built-in voltage hysteresis that helps eliminate false trips. to introduce further user-programmable hysteresis, the ltc3805-5 sources 5a out of the run pin when operation of ltc3805-5 is enabled. as a result, the falling threshold for the run pin also depends on the value of r1 and can be programmed by the user. the falling threshold for v in is therefore v in(run,falling) = v runoff ? r1 + r2 r2 ? r1 ? 5a where r1(5a) is the additional hysteresis introduced by the 5a current sourced by the run pin. when in shutdown, the run pin does not source the 5a current and the rising threshold for v in is simply v in(run,rising) = v runon ? r1 + r2 r2 note that for some applications the run pin can be con - nected to v cc in which case the v cc thresholds, v turnon and v turnoff , control operation. external run/stop control to implement external run control, place a small n-channel mosfet from the run pin to gnd as shown in figure 3. drive the gate of this mosfet high to pull the run pin to ground and prevent converter operation. selecting feedback resistor divider values the regulated output voltage is determined by the resistor divider across v out (r3 and r4 in figure 8). the ratio of r4 to r3 needed to produce a desired v out can be calculated: r3 = v out ? 0.8v 0.8v r4 choose resistance values for r3 and r4 to be as large as possible in order to minimize any effciency loss due to the static current drawn from v out , but just small enough so that when v out is in regulation the input current to the v fb pin is less than 1% of the current through r3 and r4. a good rule of thumb is to choose r4 to be less than 80k. figure 3. setting run pin voltage and run/stop control ltc3805-5 run run/stop control (optional) r1 r2 gnd 38055 f03 v in
ltc3805-5 13 38055fe applications information feedback in isolated applications isolated applications do not use the fb pin and error ampli - fer but control the i th pin directly using an opto-isolator driven on the other side of the isolation barrier as shown in figure 4. for isolated converters, the fb pin is grounded which provides pull-up on the i th pin. this pull-up is not enough to properly bias the opto-isolator which is typically biased using a resistor to v cc . since the i th pin cannot sink the opto-isolator bias current, a diode is required to block it from the i th pin. a low leakage schottky diode, or low forward voltage pn junction diode, should be used to ensure that the opto-isolator is able to pull i th down to its lower clamp. oscillator synchronization the oscillator may be synchronized to an external clock by connecting the synchronization signal to the sync pin. the ltc3805-5 oscillator and turn-on of the switch are synchronized to the rising edge of the external clock. the frequency of the external sync signal must be 33% with respect to f osc (as programmed by r fs ). additionally, the value of f sync must be between 70khz and 700khz. current sense resistor considerations the external current sense resistor (r sense in figure 8) allows the user to optimize the current limit behavior for the particular application. as the current sense resistor is varied from several ohms down to tens of milliohms, peak switch current goes from a fraction of an ampere to several amperes. care must be taken to ensure proper circuit operation, especially with small current sense resistor values. for example, with the peak current sense voltage of 100mv on the i sense pin, a peak switch current of 5a requires a sense resistor of 0.020 w. note that the instantaneous peak power in the sense resistor is 0.5w and it must be rated accordingly. the ltc3805-5 has only a single sense line to this resistor. therefore, any parasitic resistance in the ground side connection of the sense resistor will increase its apparent value. in the case of a 0.020 w sense resistor, one milliohm of parasitic resistance will cause a 5% reduction in peak switch current. so the resistance of printed circuit copper traces and vias cannot necessarily be ignored. programmable slope compensation the ltc3805-5 injects a ramping current through its i sense pin into an external slope compensation resistor r slope . this current ramp starts at zero right after the gate pin has been high for the ltc3805-5s minimum duty cycle of 6%. the current rises linearly towards a peak of 10a at the maximum duty cycle of 80%, shutting off once the gate pin goes low. a series resistor r slope connecting the i sense pin to the current sense resistor r sense develops a ramping voltage drop. from the perspective of the i sense pin, this ramping voltage adds to the voltage across the sense resistor, effectively reducing the current comparator threshold in proportion to duty cycle. this stabilizes the control loop against subharmonic oscillation. the amount of reduction in the current comparator threshold ( d v sense ) can be calculated using the following equation: d v sense = dutycycle ? 6% 80% 10a ? r slope note: ltc3805-5 enforces 6% < duty cycle < 80%. a good starting value for r slope is 3k, which gives a 30mv drop in current comparator threshold at 80% duty cycle. designs that do not operate at greater than 50% duty cycle do not need slope compensation and may replace r slope with a direct connection. figure 4. circuit for isolated feedback ltc3805-5 i th fb v cc isolation barrier gnd 38055 f04
ltc3805-5 14 38055fe applications information overcurrent threshold adjustment figure 5 shows the connection of the overcurrent pin, oc, along with the i sense pin and the current sense resistor r sense located in the source circuit of the power nmos which is driven by the gate pin. the internal overcurrent threshold on the oc pin is set at v oct = 100 mv which is the same as the peak current sense voltage v i(max) = 100 mv on the i sense pin. the role of the slope compensation adjust - ment resistor r slope and the slope compensation current i slope is discussed in the prior section. in combination with the overcurrent threshold adjust current i oc = 10a, an external resistor r oc can be used to lower the overcurrent trip threshold from 100mv. this section describes how to pick r oc to achieve the desired performance. in the discussion that follows be careful to distinguish between current limit where the converter continues to run with the i sense pin limiting current on a cycle-by-cycle basis while the output voltage falls below the regulation point and overcurrent protection where the oc pin senses an overcurrent and shuts down the converter for a timeout period before attempting an automatic restart. one overcurrent protection strategy is for the converter to never enter current limit but to maintain output volt - age regulation up to the point of tripping the overcurrent protection. operation at minimum input voltage v in(min) hits current limiting for the smallest output current and is the design point for this strategy. first, for operation at v in(min) , calculate the duty cycle duty cycle v in(min) using the appropriate formula depending on whether the converter is a boost, fyback or sepic. then use duty cycle v in(min) to calculate dv sense(vin(min)) using the formula in the prior section. for overcurrent protection to trip at exactly the point where current limit - ing would begin set: r oc(crit) = d v sense vin(min) ( ) 10a to fnd the actual output current that trips overcurrent protection, calculate the peak switch current i pk(vin(min)) from: i pk vin(min) ( ) = 100mv ? d v sense vin(min) ( ) r sense then calculate the converter output current that corre - sponds to i pk(vin(min)) . again, the calculation depends both on converter type and the details of converter design including inductor current ripple. for minimum input volt - age, r oc(crit) produces an overcurrent trip at an output current just before loss of output voltage regulation and the onset of current limiting. note that the output current that causes an overcurrent trip is higher for higher input voltages but that an overcurrent trip will always occur before loss of output voltage regulation. if desired to meet a specifc design target, an increase in r oc above r oc(crit) can be used to reduce the trip threshold and make the converter trip for a lower output current. this calculation is based on steady-state operation. de- pending on design, overcurrent protection can also be triggered during a start-up transient, particularly if large output flter capacitors are being charged as output voltage rises. if that is a problem, output capacitor charging can be slowed by using a larger value of ssflt capacitor. it is also possible to trip overcurrent protection during a load step especially if the trip threshold is lowered by making r oc > r oc(crit) . another overcurrent protection strategy is keep the con - verter running as current limiting reduces the duty cycle and the output voltage sags. in this case, the goal is often keep the converter in normal operation over as wide a range as possible, including current limiting, and to trigger the figure 5. circuit to decrease overcurrent threshold ltc3805-5 oc gate i sense r sense r slope i oc = 10a i slope gnd 38055 f05 r oc
ltc3805-5 15 38055fe applications information overcurrent trip only to prevent damage. to implement this strategy use a value of r oc smaller than r oc(crit) . this also reduces sensitivity to overcurrent trips caused by transient operation. in the limit, set r oc = 0 and connect the oc pin directly to r sense . this causes an overcurrent trip near minimum duty cycle or around 6%. in some cases it may be desirable to increase the trip threshold even further. in this strategy, the converter is allowed to operate all the way down to minimum duty cycle at which point the cycle-by-cycle current limit of the i sense pin is lost and switch current goes up propor - tionally to the output current. figures 6 and 7 show two ways to do this. figure 6 is for relatively low currents with relatively large values of r sense . using this circuit the overcurrent trip threshold is increased from 100mv to: v oc = r sense1 + r sense2 r sense1 100mv where it is assumed that the values of r sense1 and r sense2 are so small that the i oc = 10a threshold adjust- ment current produces a negligible change in v oc . for larger currents, values of the current sense resistors must be very small and the circuit of figure 6 becomes impractical. the circuit of figure 7 can be substituted and the current sense threshold is increased from 100mv to: v oc = r1 + r2 r1 100mv where the values of r1 and r2 should be kept below 10 w to prevent the i oc = 10a threshold adjustment current from producing a shift in v oc . external soft-start fault timeout the external soft-start is programmed by a capacitor c ss from the ssflt pin to gnd. at the initiation of soft-start the voltage on the ssflt pin is quickly charged to 0.7v at which point gate begins switching. from that point, a 6a current charges the voltage on the ssflt pin until the voltage reaches about 2.25v at which point soft-start is over and the converter enters closed-loop regulation. the soft-start time t ss(ext) as a function of the soft-start capacitor c ss is therefore: t ss(ext) = c ss 2.25 ? 0.7v 6a after soft-start is complete, the voltage on the ssflt pin continues to charge to about a fnal value of 4.75v. note that choosing a value of c ss less than 5.8nf has no effect since it would attempt to program an external soft-start time t ss(ext) less than the mandatory minimum internal soft-start time t ss(in) = 1.8ms. if there is an overcurrent fault detected on the oc pin, the ltc3805-5 enters a shutdown mode while a 2a current discharges the voltage on the ssflt pin from 4.75v to about 0.7v. the fault timeout t fto(ext) is therefore: t fto(ext) = c ss 4.75v ? 0.7v 2a at this point, the ltc3805-5 attempts a restart. in the event of a persistent fault, such as a short-circuit on the converter output, the converter enters a hiccup mode where it continues to try and restart at repetition rate determined by c ss . if the fault is eventually removed the converter successfully restarts. figure 6. circuit to increase the overcurrent threshold for small switch currents figure 7. circuit to increase the overcurrent threshold for large switch currents ltc3805-5 oc gate i sense r sense1 r sense2 r slope gnd 38055 f06 i oc = 10a i slope ltc3805-5 oc gate i sense r1 r2 r slope gnd 38055 f07 r sense i oc = 10a i slope
ltc3805-5 16 38055fe typical applications figure 8. 5.5v to 40v to 12v/2a sepic converter ltc3805-5 0.1f 4.7f bas516 10k 6.8nf gnd i th ssflt gate fb run fs v cc oc i sense sync 1 2 3 4 5 10 9 8 7 6 11 t1 10f 50v d1 pds760 4.56h bh510-1009 c in 10f 50v c out 47f 16v r4 7.15k 69.8k 80.6k 3.01k r sense 0.005 38055 f08 q1 hat2266 v out 12v 2a r3 100k 301w 221k 57.6k v in 5.5v t0 40v pdz6.8b mmbt6428lt1 ? ? load current (a) 0.01 40 efficiency (%) power loss (w) 50 60 70 80 0.1 1 10 38055 ta04b 30 20 10 0 90 100 0.5 1.0 1.5 2.0 2.5 0 3.0 3.5 5.5v 10v 20v 30v 40v efficiency power loss effciency and power loss vs load current
ltc3805-5 17 38055fe typical applications figure 9. isolated telecom supply: 18v to 72v input to 3.3v/3a output effciency and power loss vs load current and v in load current (a) 0.01 60 efficiency (%) power loss (w) 80 100 0.1 1 10 38055 ta03b 40 50 70 90 30 20 2.0 3.0 4.0 1.0 1.5 2.5 3.5 0.5 0 18v 36v 48v 60v 72v efficiency power loss v in oc comp fb gnd opto 75k 15.8k 1f 0.47f 100k 47pf 22.1k 2200pf 250vac 274 2.2nf 221k bas516 bas516 d2 bas516 fdc2512 v in v cc v cc 11 5 4 3 2 1 6 7 8 2 3 4 pa1277nl 1 7 6 5 8 d1 pds1040 100f 6.3v 100f 6.3v 100f 6.3v 9 1 3 2 6 4 5 10 r bias 402 10w bas516 ba760 68 150pf 200v pdz6.8b 6.8v mmbta42 v in ? 6.8k 221k u1 ltc3805-5 i th gnd ssflt run gate oc i sense sync fs fb v cc 56k 38055 f09 0.04 v out + 3.3v 3a v out ? ps2801-1-k u2 lt4430 v in + 18v to 72v 2.2f 100v 2.2f 100v 0.022f 1f 221k 3.01k
ltc3805-5 18 38055fe dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev b) mse package 10-lead plastic msop (reference ltc dwg # 05-08-1664 rev c) package description 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dd) dfn rev b 0309 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.70 0.05 3.55 0.05 package outline 0.25 0.05 0.50 bsc msop (mse) 0908 rev c 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ? 0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 1 2 3 4 5 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8910 10 1 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 2.083 0.102 (.082 .004) 2.794 0.102 (.110 .004) 0.50 (.0197) bsc bottom view of exposed pad option 1.83 0.102 (.072 .004) 2.06 0.102 (.081 .004) 0.1016 0.0508 (.004 .002) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.05 ref 0.29 ref
ltc3805-5 19 38055fe information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number d 04/10 updates to absolute maximum ratings changes to electrical characteristics table updates to note 2 update to pin 11 in pin functions edits to start-up shutdown in operation section change to typical application updated related parts table 2 3 4 7 9 17, 20 20 e 05/11 added mp-grade part. refected throughout the data sheet 1-20 (revision history begins at rev d)
ltc3805-5 20 38055fe linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2008 lt 0511 rev e ? printed in usa related parts typical application 5v to 40v to 12v/1a nonisolated flyback converter load current (a) 0.01 50 efficiency (%) power loss (w) 70 90 0.1 1 10 38055 ta02b 30 40 60 80 20 10 4 6 8 2 1 3 5 7 0 5.5v 10v 20v 30v 40v effciency and power loss vs load current 75k 3.01k 4.7f 100f 16v 51.1k 47pf c ss 0.1f d1 ups840 fdc2512 v cc 11 5 4 3 2 1 6 7 8 1 4 10 8 7 9 9 10 220 150pf 200v 38055 ta02 2.2f 100v v in 5v to 40v v cc u1 ltc3805-5 i th gnd ssflt run gate oc i sense sync fs fb v cc 100f 16v r sense 0.005 v out 12v 1a 470pf 100pf 20k 3.65k 2.2f 100v 10k 6.8v pdz6.8b 680 d2 bas516 t3772 mmbta42 part number description comments lt3748 100v no opto flyback controller 5v v in 100v, boundary mode operation, msop-16 with extra high voltage pin spacing lt3758 boost, flyback, sepic and inverting controller 5.5v v in 100v, 100khz to 1mhz programmable operating frequency, 3mm w 3mm dfn-10 and msop-10e lt3575 no opto-isolated flyback with 60v integrated switch 3v v in 40v, up to 14w, boundary mode operation, tssop-16e ltc3803/ltc3803-3/ ltc3803-5 flyback dc/dc controller with fixed 200khz or 300khz operating frequency v in and v out limited only by external components, 6-pin thinsot? package ltc3873/ltc3873-5 no r sense ? constant frequency flyback, boost, sepic controller v in and v out limited only by external components, 8-pin thinsot or 2mm w 3mm dfn-8 packages lt3825 no opto-isolated synchronous flyback controller v in 16v to 75v limited by external components, up to 60w, tssop-16e

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